ISO/IEC 18372:2004
2004-12
Resumen
The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-toboard communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.
Informaciones generales
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Estado: PublicadoFecha de publicación: 2004-12Etapa: Norma Internacional confirmada [90.93]
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Edición: 1Número de páginas: 405
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Comité Técnico :ISO/IEC JTC 1/SC 25ICS :35.100.30
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